Wave Issue 0303 2/7/03 Article 4-01

***Fujitsu Announces Fast New CMOS DAC
(January 31)

Fujitsu Microelectronics America, Inc. (FMA) today announced the
MB86064 Dual 14-bit 800MSa/s Digital to Analog Converter (DAC).
This is the first Application Specific Standard Product (ASSP)
based on its next-generation DAC technology.

Until today Fujitsu has been providing customers with early
access to their next-generation DAC technology through mixed
signal ASIC (MS-ASIC) solutions. The move to provide an ASSP
solution will enable applications where a custom approach is
either not required or not justified.

As well as improved performance from circuit designs, the product
has a number of features, ranging from the on-chip vector
memories (which enhance system integration and test) to next-
generation Segment Shuffling (which further improves dynamic
performance). The vector memories enable waveforms to be
downloaded and executed on-chip. For device test and evaluation
this alleviates the need for a high-speed data generator,
according to Fujitsu, while in a final system application they
are ideal for implementing tests on the subsequent analog signal
chain.

Analog performance at high output frequencies is enhanced by
current switch and switch driver designs that provide constant
data-independent switching delay, reducing jitter and distortion.
In four-carrier W-CDMA applications, ACPR of 70dBc can be
achieved with direct-IF generation at 300MHz, with even higher
performance at lower output frequencies.

Fujitsu believes that direct-IF architectures can now demonstrate
cost competitiveness to more traditional direct modulation
architectures, while avoiding their inherent drawbacks.
Bandwidths up to 100MHz can now be generated directly at these
high IFs, sufficient to implement the entire UMTS band with
digital pre-distortion.

Fujitsu stated that the Segment Shuffling is an enhancement over
techniques introduced in the MB86060 and MB86061 DAC ASSPs. This
improves performance to the level sought after for next-
generation systems and high direct-IF architectures by moving
distortion products out-of-band and reducing device-to-device
variation.

Implemented in Fujitsu's mixed signal CS80A 0.18 micron CMOS
process, the dual DAC core, combined with LVDS data inputs and a
versatile serial control port, provides a DAC solution.
Generating and driving the data for such a DAC has traditionally
been restricted to ECL-based technology.

However, the provision of a LVDS interface, combined with the
advance in data-generating capabilities of ASSPs, ASICs and
FPGAs, enables cost-effective, realizable solutions. In
particular, clock-to-data timing across the data interface can be
guaranteed by using FPGAs with Phase Locked Loop (PLL) or Delay-
Locked Loop (DLL) clock generators and external reference clock
loop-back.

The MB86064 is housed in Fujitsu's enhanced fine-pitch ball grid
array (EFBGA) package. The EFBGA range has been developed
specifically to meet the needs of high-performance mixed signal
devices. Benefits include optimized signal routing within the
package, easier PCB tracking and excellent thermal properties
assisted by a thermal ball array directly under the device. Using
the 120-ball variant, the package measures 12mm x 12mm.

Customer development kits and sample devices are available today.
Mass production is scheduled for 3Q CY2003.

www.fma.fujitsu.com/