Wave Issue 0201 1/11/02 Article 4-02

***Altera and TSMC Deliver 0.13-Micron All-Copper Interconnect
PLD
(January 7)

Altera and Taiwan Semiconductor Manufacturing Company (TSMC) have
announced a programmable logic device (PLD) built on a 0.13-
micron semiconductor fabrication process using copper for all
layers of metal interconnect. The Altera's APEX II EP2A70 device
was developed in partnership with TSMC.

Copper interconnect layers in integrated circuits (ICs) offer
lower electrical resistance over traditional aluminum/tungsten
metal layers, reducing interconnect delays up to 40 percent and
improving performance. Migration to a 0.13-micron semiconductor
fabrication process combined with all-layer copper interconnects
further enhances the benefits by reducing die sizes, yielding
more dice per wafer and increasing device performance.

The APEX II devices are Altera's high-performance, high-density
PLD family for system-on-a-programmable-chip (SOPC) applications.
Building on the APEX architecture, the APEX II device family
places programmable logic directly in the datapath of high-
performance communication applications. APEX II devices support
I/O interfaces such as RapidIO, Utopia IV, POS-PHY Level 4,
HyperTransport and Flexbus.

Features include dedicated serialization/deserialization (SERDES)
and Clock data-synchronization (CDS) circuitry that make 1 Gbps
differential signaling possible for high-speed I/O capabilities,
needed in high performance communications applications. The APEX
II architecture also provides up to 1.1 Mbits of internal memory
creating a solution for memory-intensive applications, such as
packet processing.