Wave Issue 2003 1/19/00 Article 1-02

***Mentor Graphics Seamless Co-Verification Environment to
Support Infineon Technologies TriCore 32-Bit Unified Processor
for Embedded Systems
(January 19)

Mentor Graphics announced that it will provide co-verification
support for the TriCore Unified Processor from Infineon
Technologies, an advanced 32-bit architecture for embedded
systems. Under the terms of an agreement, Mentor Graphics will
deliver a Seamless Co-Verification Environment (CVE) processor
support package (PSP) for the TriCore Unified Processor, based
upon technology licensed from Infineon. The Seamless PSP for
TriCore provides embedded system designers with the ability to
co-verify any system-on-chip or system-on-board that embeds the
TriCore Unified Processor.

Mentor Graphics Seamless CVE allows design teams to perform co-
verification before creating a physical prototype, enabling early
detection and correction of errors in the hardware/software
interface. Seamless CVE shortens the development time for
embedded systems, such as system-on-chip and system-on-board,
reduces the number of hardware prototype iterations and
accelerates the debug of all levels of software developed for the
target system.

The TriCore Unified Processor architecture utilizes on-chip
memory and nanosecond context switching to support real-time
control and digital signal processing (DSP) tasks in a single
core. It's 32-bit RISC architecture provides concurrent
processing of both control and DSP functions, with C and C++
access to DSP functions and the real-time performance required
for embedded systems.

Mentor will develop and deliver a Seamless PSP for TriCore
Unified Processor designs, incorporating the Infineon cycle-
accurate Instruction Set Simulator Model, TSIM+, already
available to developers writing code for the TriCore
architecture. The PSP includes integration with high-level
debuggers supported by the TriCore Unified Processor development
tool chain, including the Mentor XRAY Debugger.

Production shipments of Mentor Graphics' Seamless CVE 4.0 for the
TriCore architecture will start Q1 of 2000 running on HP and Sun
workstations. Pricing of the Seamless PSP for the Infineon
TriCore Unified Processor is listed at $30,000.