Wave Issue 2000 1/3/00 Article 8-01

***Transeda Streamlines Design Verification Process
(December 6)

According to DACafe, TransEDA introduced Verification Navigator,
an integrated design verification environment that provides code
coverage, test suite optimization, state machine coverage, and
circuit activity analysis for Verilog, VHDL, and dual-language
designs. Verification Navigator's structured verification
methodology provides designers the information needed to answer
many critical questions, such as:

How well do my test benches verify each block in the design?
Where should I focus additional verification effort?
Are any of my vector sets redundant?
Am I running the most productive vector sets first?
Have I simulated all transitions in all of the state machines in
my design?
How well do my low-power design techniques reduce circuit
activity?

Verification Navigator is built on the foundation of TransEDA's
HDLCover, VeriSure and VHDLCover code coverage tools. With these
and other capabilities integrated in Verification Navigator,
designers now can perform multiple verification tasks from a
common, interface.

The heart of Verification Navigator is VN-Cover, the single-
kernel, dual-language, simulator-independent code coverage tool.
The single-kernel capability, available for the first time in
Verification Navigator, allows code coverage to be generated from
a single simulator run on dual-language simulators. VN-Cover
provides coverage metrics to improve the verification of the
design. VN-Cover not only shows you how many times each line was
executed, but it also provides a set of coverage metrics such as
variable toggle, branch and condition, statement, path and
variable trace.

Verification Navigator includes an integrated test-suite
optimization tool called VN-Optimize. VN-Optimize sorts test
sets, allowing the most productive tests to be run first. With
this capability, Verification Navigator not only selects the
fewest number of tests needed to achieve good coverage, but also
assesses the execution time, therefore determining the minimum
time needed to achieve good coverage.

Verification Navigator also includes VN-State, a tool that
provides finite state machine (FSM) coverage data. VN-State
automatically extracts an FSM diagram from the HDL code and
calculates transition coverage metrics of the state machine based
on simulation results. The fully editable state diagram offers
both insight into the design as well as graphical documentation
of the FSM. The transition coverage metrics help the designer to
better understand how well each FSM has been exercised during
simulation.

A tool for circuit activity analysis called VN-Activity is also
included. VN-Activity enables designers to measure the
effectiveness of low-power design techniques by analyzing circuit
activity during RTL simulation on a block-by-block basis. It
enables a wide exploration of the low-power design space without
going through the time and effort to generate detailed power
estimates.

Verification Navigator is easy to add to existing verification
environments. The on-line documentation can guide first time
users through operation. The tool does not require changes to the
design style or source code, and has been fully tested with
industry leading simulators, including ModelSim, VCS, VSS,
Affirma-NC and Verilog-XL.

Verification Navigator is available immediately with the U.S.
list price starting at $20,000. The base configuration includes
VN-Cover (single language), VN-Activity, VN-State and an entry-
level version of VN-Optimize. Dual-language and language-neutral
options are available as is the full version of VN-Optimize.
Existing HDLCover, VeriSure and VHDLCover customers currently
under maintenance will automatically receive free upgrades to
Verification Navigator.

www.transeda.com