Wave Issue 2000 1/3/00 Article 6-01

***Aspec Technology Rolls Out EDA Software Tools
(December 15)

According to DACafe, Aspec Technology an provider of productivity
solutions for the Electronic Design Automation (EDA) and Product
Data Management (PDM) markets, has announced a technology to
address statistically-based worst case interconnect modeling for
deep submicron designs. The Statistically-based Worst case
Interconnect Model (SWIM) generator and Interconnect delay
Calculator (InterCal) products will give semiconductor
manufacturers the ability to enhance performance, maximize
capacity, optimize power consumption and improve overall yield by
allowing designers to use more accurate worst case interconnect
models.

SWIM and InterCal provide accurate 2-D and 3-D statistically
based worst case interconnect modeling and pre-layout
interconnect data for deep submicron design and process
development. Most manufactures use worst-case process variations
(skew corner worst case model), which provide pessimistic models,
and therefore causes unrealistic design margins for chip
designers. By using statistically based worst-case interconnect
modeling, an accurate estimation can be made of the process
variation and therefore designers can take greater advantage of
deep submicron technology without the risk of failing chips.

www.aspec.com