Wave Issue 2000 1/3/00 Article 5-02

***Cadence Methodology Powers Samsung Electronics' Advanced SOC
Design Environments
(December 16)

Cadence Design Systems announced that Samsung Electronics has
adopted and integrated the Cadence System Level Constraint (SLC)
flow into its ASIC design environment. A collaborative effort
between Samsung Electronics and Cadence created a timing-driven,
concurrent optimization methodology based on the SLC flow and
Samsung Electronics' proprietary tools.

This achievement is the result of a growing, strategic
relationship being forged between the two companies, and is the
latest in a series of collaborations for Cadence Methodology
Services. The timing convergent flow is a component of the block-
based design and platform-based design methodologies critical to
system-on-a-chip (SOC) design. Cadence just announced the
delivery of block-based design and platform-based design
methodologies and tool flows to the Alba Centre in Scotland.

The patent-pending SLC flow features Cadence's deep submicron
(DSM) tools, which rely on proven timing control, logic
optimization, and area conserving algorithms. Samsung Electronics
has been deploying the methodology throughout its worldwide
design centers. This approach leverages Cadence's SLC flow to
ensure first-pass, all-path timing closure. Cadence Methodology
Services helped strengthen the partnership by working together
with Samsung Electronics' development teams to help integrate
Samsung's tools with the SLC technology, achieving the optimum
production flow in the shortest time possible. The environment
provides Samsung Electronics' ASIC customers with solutions for
the problems facing designers: hierarchical design support, a
convergent design methodology, and rapid turnaround of high-
complexity designs.