Wave Issue 2000 1/3/00 Article 3-01

***Transeda Boosts IC Designers Productivity with State Machine
Verification Environment
(December 6)

According to DACafe, TransEDA introduced State Navigator, a
finite state machine (FSM) design, debug and verification
environment for Verilog and VHDL designs. State Navigator enables
designers to simultaneously debug multiple interacting state
machines, in contrast to FSM capture tools with limited or no
debug capability. Finite state machines are one of the most
common constructs in IC designs. They form the core of many
networking, telecommunications and bus protocols as well as the
heart of most control circuitry.

As ICs become more complex, the number and size of FSMs grows,
and the interaction between FSMs becomes increasingly difficult
to predict or verify. State Navigator provides interactive debug
of the state machines' functionality, verifies their behavioral
specification, performs a static verification of the FSM
structures, and provides detailed FSM coverage data. State
Navigator, based upon TransEDA's previous StateSure product,
extends the solution with support for additional Verilog and VHDL
FSM coding styles.

State Navigator also adds a path analysis and verification
feature that helps designers quickly identify untested corner
cases in designs containing multiple, communicating state
machines. The product features a flow-based user interface and an
enhanced state diagram layout engine for quickly generating easy-
to-read displays.

State Navigator provides a way to interact with complex FSM
designs during the design phase, using simulation results to
animate the state diagram display. Large amounts of simulation
data are presented in an easy-to-interpret format, enabling
designers to identify unexpected behavior in their design. Any
number of state machines may be displayed together and
interactions between them are visible as highlighted states and
transitions move from one FSM to the next. Users can single-step
forward or backward in simulation time and can jump to any point
in time.

State Navigator enables users to create and verify a behavioral
specification of their FSMs in terms of sequences. Sequences
allow designers to specify the behavior of the FSMs at a level
higher than the hardware description language (HDL) source code,
and then check the HDL code against the specified sequences. With
this capability, design and verification engineers can determine
if an FSM conforms to the specification. State Navigator analyzes
simulation results and identifies which sequences have been fully
verified and which are still uncovered.

State Navigator provides several static checks of FSM designs
even before simulation is run. This enables very quick detection
and correction of common design mistakes before developing
extensive test suites. Once the FSM is automatically derived from
the Verilog or VHDL source code, State Navigator identifies any
dead states, unreachable states or overwritten transitions and
generates a state diagram display. A source code window allows
for cross probing between textual and graphical displays of the
FSM. The state diagram display is fully editable and provides
PostScript output for graphical documentation of the FSM.

Building on TransEDA's strengths in code coverage reporting,
State Navigator provides additional insight into the coverage of
the FSMs contained within the design. Transition coverage is
reported in tabular format, as well as by color-coding the arcs
in the state diagram display. Transition coverage gives designers
feedback on the quality of the verification test suite.

Once 100% transition coverage has been achieved, designers can
move on to the next level verification - path coverage. For path
coverage data, State Navigator identifies all possible paths
through a state machine. After simulation, State Navigator
reports which paths have been exercised. This enables the
designer to identify untested paths in the FSM and to generate
tests to cover the missing paths. Designers can see productivity
gains with State Navigator since it does not require changes to
design style or source code, and has been fully tested with
simulators, including ModelSim, VCS, Affirma-NC and Verilog-XL.
State Navigator runs on both UNIX and Windows-NT platforms.

State Navigator is available immediately with the U.S. list price
starting at $25,000. Existing StateSure customers currently under
maintenance will automatically receive free upgrades to State
Navigator.

www.transeda.com