Wave Issue 9039 X/XX/99 Article 10-01

***Fujitsu introduces IPSymphony design environment
(March 30)

Fujitsu Limited’s WorldWide System LSI Technology (WWSLT) group
introduced IPSymphony, the next generation of Fujitsu’s chip
design environment. Developed primarily to address the
complexities of System On a Chip (SOC) design in a global
environment, IPSymphony is expected to reduce turnaround time by
40 to 60 percent, while improving the quality of first-time
silicon. IPSymphony will be the foundation for all Fujitsu design
environments worldwide.

IPSymphony is built on two developments, Common Software
Interface (CSI) and Web-Based Engineering (WBE). CSI makes it
possible to integrate Fujitsu and Independent Software Vendor
(ISV) tools together. WBE is the realization of the “work
anywhere, anytime” concept.

IPSymphony provides a complete system-level design environment to
ensure success from concept to prototype for IP/block-based
design. The technology addresses the increased planning and
estimation required early in the process to handle area, power,
testability, signal integrity and timing requirements for SOC
design. IPSymphony facilitates high-level abstraction using
C/C++, RTL and hardware / software partitioning, effectively
elevating silicon issues to the abstract level. The result is a
reduction in the number of iterations required to meet the chip
design requirements. Functional and manufacturing verification,
including automated test-bench generation, built-in self test,
formal verification and hardware / software co-verification,
together with advanced SOC test methodologies, will test the
design and decrease test time.

In the physical implementation, IPSymphony can handle the large
SOC design (5-10 million gates) with high performance (over 600
MHz). Timing-driven, stage-based constraints and the ability to
handle hierarchical designs will shorten the design cycle.

To address the logistics of coordinating multiple design teams
and the increase in data, IPSymphony incorporates data management
into each step of the methodology. Revision control, data
accessibility and logistics are inherent in the software
architecture; documentation and scheduling are automated. The
chip status and status of the individual blocks are accessible,
enabling concurrent engineering.

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