Wave Issue 9036 4/6/99 Article 5-01

***Fujitsu releases low cost Single-Chip MPEG-2 Decoder
(March 15)

Fujitsu introduced a single-chip MPEG-2 video and audio decoder
available integrating transport demultiplexer and 32-bit RISC
CPU. Decoding and transport demultiplexing are implemented in
hardware, allowing customers to use the complete CPU power to
generate graphic and EPGs (electronic program guides).

Compliant to DVB standards, the integrated MB87L2250 decoder is
designed for use in terrestrial, cable and satellite set-top
boxes.

The device uses a 2.5 frame architecture which means that the B-
pictures do not require to be entirely stored in memory, allowing
high resolution pictures and graphics to be produced using just
16M-bit of SDRAM for MPEG decoding, OSD and section data
buffering.

Designed at Fujitsu’s European Multimedia Design Centre in
Frankfurt and fabricated in 0.35mm process technology, the device
uses ASIC building block based design techniques. Full support
for customers is available from the Design Centre.

The decoder also provides features like letterbox format
conversion or teletext insertion into the VBI. The decoder is
enclosed in an FTP-208P package.

The MB87L2250 will be available in volume quantities during Q199
together with an evaluation board and low level software driver
to initialize the program.

Additional features:
- DVB de-scrambler for TS and PES
- Support for 32 PIDs
- Flexible section processing
- Two smart card interfaces
- 32-bit RISC CPU: 4 stage pipeline; 1kbyte I-Cache

Commercial development tools available
- Individual buffer allocation for each stream
- Supports 3:2 pull down

www.fujitsu-ede.com/