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Silicon Access Breaks the Performance Bottleneck for True
System-Level Chips
(March 10)
Silicon Access Inc claims to provide true system-level
integration capabilities with proprietary deep submicron
embedded DRAM technology. This embedded DRAM capability,
combined with the Company's 0.25-micron I/O cells, extensive
standard cell libraries, ASIC design flow expertise and physical
design services, allows them to put the pieces in place to
accomplish true system-level integration.
Why Embedded DRAM?
The company states that there will be an increasing need to
embed DRAM and logic on system-level chips with the
proliferation of high-volume consumer and networking
applications driven by performance and power considerations. The
majority of these chips will be manufactured by deep submicron
foundries that are tightly linked to an IP provider such as
Silicon Access with extensive embedded DRAM capabilities and
advanced 0.25-micron standard cell libraries.
True system-level chips provide many critical advantages. Memory
embedded on-chip with logic improves overall system performance
and reliability, and reduces the system cost and time-to-market
over discrete solutions. It also decreases power consumption
that significantly increases battery life in portable
applications. This advantage is magnified with embedded DRAM
where macro size is 10 to 20 times smaller than a comparable
SRAM macro. Embedded DRAMs can eliminate the pad-limited design
problem. With the increased densities available today from the
deep submicron foundries, a typical application using a few
hundred thousand gates of logic will result in an expensive pad-
limited chip. The company feels that by adding embedded memory
it not only better utilizes the chip density, it also reduces
the number of I/Os required for interface between the memory and
logic chips. This will speed up the design cycle, improve
overall systems performance and decrease overall system cost.
Silicon Access will not only provide a full range of IP memory
configurations for embedded DRAMs, but also for SRAMs and ROMs.
The Company will have the first one-transistor DRAM compiler,
allowing for unlimited memory configurations targeted to
specific design applications. This compiler will give the
customer the combined benefits of low-cost memory and high-
performance logic-key to many high-volume consumer applications.
Silicon Access offers two additional capabilities over other IP
solutions. Both stem from the founders' management experience in
the ASIC, EDA and DRAM industries. Successful management of
large complex designs requires a fully developed IC design flow
with all of the methodologies and disciplines in place. It also
requires a full range of back-end design services that tightly
link to the timing requirements defined during front-end design.
Without these two elements, there are many risks of costly and
time-consuming design iterations. Silicon Access feels they
understand the importance of these issues and that they have all
the components to assure successful IP-based system-level chip
design.
Founded in 1997, Silicon Access is headquartered in San Jose at
2025 Gateway Place, Suite 380, San Jose CA 95110-1014. Phone
(408)441.7390, Fax (408)441-7370.
www.SiliconAccess.com
Synopsys Announces Multimillion Gate VHDL System Verification
Solution
(March 16)
Synopsys Inc. announced support for a cycle-based simulation
interface for hardware/software co-verification. The ability to
use Cyclone VHDL, Synopsys' cycle-based simulator, with the
company's industry-leading Eagle hardware/software co-
verification tools, gives designers the capacity needed to
simulate entire systems that, until now, were too large to
handle with VHDL event-based simulation. The system verification
solution has successfully validated a customer's 24-processor
network switching system comprising of multiple system-on-a-chip
(SoC) designs plus embedded software. Cyclone can simulate the
entire system -- 5.5 million equivalent gates.
Cyclone VHDL is a Direct RTL, cycle-based simulator that takes
advantage of the Synopsys' synthesis technology and provides
superior performance and capacity over traditional VHDL event-
simulation technologies. A copy of Synopsys’ VHDL System
Simulator (VSS) accompanies each copy of Cyclone for source-code
level debugging and VITAL sign-off requirements.
The Eagle co-verification tools enable the earliest possible
development and integration of embedded systems described in
Verilog or VHDL. Instead of requiring the designer to wait for
physical prototypes, Eagle bridges the hardware simulation and
software development environments, making it possible to
integrate hardware and software functionality much earlier in
the design cycle. An open architecture makes it easy for third
parties to link their tools to the Eagle environment, providing
unequaled support for the hardware and software tools designers
use today and a straightforward integration path for the future.
Pricing for Cyclone VHDL and Eagle starts at U.S. $45,000 and
$60,000, respectively. The new Cyclone/Eagle interface is
available now at no charge to Cyclone and Eagle customers on
current maintenance contracts.
www.synopsys.com
Synopsys Announces VCS 4.1
(March 16)
Synopsys Inc. announced the release of Chronologic VCS 4.1. VCS
4.1 reduces overall verification time on multimillion gate
designs at all levels of abstraction. Leveraging the performance
leadership of the RoadRunner technology introduced in VCS 4.0,
new features of VCS 4.1 include: performance increases of up to
2X and memory capacity improvements of up to 5X which
incorporate new optimization algorithms for gate and transistor-
level primitives as well as enhancements for gate-level designs
providing up to 20X improvements on compiler speed.
Design verification requires high performance and capacity
throughout the entire process from the early design exploration
and functional simulation phases to the final sign-off stages.
Providing an environment complete with model development,
advanced debugging techniques, and comprehensive sign-off
capabilities, VCS 4.1 is the ideal verification solution.
VCS 4.1 delivers advanced simulation technology for high-level
design methodology on multimillion gate designs at all levels of
behavioral, RTL, gate and transistor abstraction -- raising the
bar for Verilog performance and memory capacity.
VCS 4.1 is available immediately. Pricing starts at U.S. $40,000
for networked licenses. Synopsys VCS customers with current
software maintenance will automatically receive the software
update at no additional cost.
VCS 4.1 is available on most UNIX workstations; Solaris, SunOS,
HP-UX, DEC Alpha, IBM RS6000 and SGI; Windows 95- and Windows
NT-based systems; and mixed UNIX/NT floating network license
support.
www.synopsys.com.
Cadence and Motorola Cooperate to Deliver Advanced System
Simulation Technology
(March 17)
Motorola has licensed an internal design technology used to
manage system simulation and virtual prototyping to Cadence
Design Systems Inc. for servicing the general market. The
simulation manager enables companies to cut design costs while
speeding time-to-market with the simultaneous development of
hardware and software (HW and SW). The companies will cooperate
to further define existing APIs for communication between models
of integrated circuits and the simulation manager.
Motorola refers to the entire suite of models, simulation
manager, virtual prototyping tools and APIs as SIMez System
Simulation and Virtual Prototyping. Under this agreement,
Cadence and Motorola will provide customers with an advanced HW
and SW system simulation manager that interfaces Cadence's
family of logic simulators with a portfolio of processor and
peripheral models. Using the simulation manager along with a
simulation engine and software debugger, embedded system
designers can concurrently develop and optimize hardware and
software system components.
These models conform to IEEE simulation standards and can be
used in a wide variety of simulation environments. The
simulation management technology offered by this software
integrates with Cadence's verification flow enabling customers
to reuse system test benches at a variety of design abstraction
levels.
Motorola offers models of market leading microcontrollers and
microprocessors, including the 68HC08, 68HC12, and MPC500
PowerPC plus a wide range of peripherals. The models have been
tested against the original silicon test vectors and proven to
be accurate to the clock edge, a new feature available in
Motorola models. The models can also be run at a near Clock
Cycle Accurate level for faster simulation.
www.cadence.com.
Silicon Architects of Synopsys Delivers Industry's Largest
Silicon Library in New CBAII Technology
(March 18)
Silicon Architects of Synopsys announced a synthesis-rich
silicon library with over 1,000 logic cells implemented in its
new CBAII technology, which includes the core library, memory
compilers and fine pitch I/Os. A significant enhancement to the
density-efficient Cell-Based Array (CBA) technology, CBAII is
further optimized for deep-submicron designs -- 0.25-micron and
smaller and provides greater than 15% increase in density over
CBA.
CBAII is an ideal platform for design reuse, providing a smooth
embedding process to host legacy intellectual property (IP) and
ensuring predictability for soft IP by hardening it to enable
portability for subsequent implementations. The capabilities of
this new technology allow customers to get more chips from each
wafer faster, maximizing CBA customers' return on investment.
SoC design is dependent on design reuse which is dependent on IP
portability. Features of the CBAII architecture and common
library ensure that designs implemented in CBAII are inherently
portable. Implementing designs in the CBAII technology offers
unique advantages for several types of IP. The smooth tool flow
makes CBAII an ideal platform for embedding and reusing legacy
IP.
The performance of soft IP is more predictable in all CBAII
libraries, once it has been implemented in one CBAII library.
For these "hardened" soft IP blocks, CBAII enables portability
across all CBAII processes, providing IP developers with an
efficient method of design reuse.
Another key factor to SoC design is the ability to maximize
utilization of silicon. CBAII architecture delivers better
density through a library optimized for four or more metal
layers that leverages a re-designed cell layout to support
stacked vias and salicide semiconductor processes. In addition,
the CBAII library provides optimized cell sets for high
performance and low power, including views for Synopsys Power
Compiler and Synopsys DesignPower. CBAII further reduces chip
development costs through metal programmability which speeds
turn times for engineering change orders and allows for rapid
development of derivative products
CBAII technology licenses and consulting are available now
Silicon Architects of Synopsys provides ASIC design technology
to leading ASIC and semiconductor vendors and system companies
worldwide. These licensees represent over 65% of available
commercial fab capacity and have implemented over 500 designs in
CBA. CBAII provides the same portability, cost and time-to-
market advantages as the original CBA technology plus an
extremely efficient architecture for increased density in deep
submicron processes.
www.synopsys.com.
Indus Becomes Integrated Intellectual Property and Introduces
Comprehensive AGP Solution for High Bandwidth 3D Graphics
Designs
(February 16)
The founders of Indus Consulting announced they have changed
their company name to Integrated Intellectual Property, Inc. to
reflect a new business direction and technology focus on the
market for "soft" intellectual property (IP). They are also
preparing to bring to market a family of synthesizable hardware
description language (HDL) cores for I/O and interconnect
functions based on industry standards. The company's reusable
register-transfer level (RTL) IP products will be accompanied by
comprehensive verification environments and expert integration
services to provide a complete IP solution to system houses,
foundries, and integrators creating systems-on-silicon for
computer, communication, and consumer electronics applications.
Integrated Intellectual Property, Inc. also introduced a new
"soft core" solution for developing and implementing AGP designs
for semiconductor, systems, and consumer electronics companies
building high bandwidth 3-D processors and computer systems with
advanced graphics capability.
The SuperAGP product family features highly modular target and
master synthesizable cores as well as robust functional
verification environments. Design teams using Integrated
Intellectual Property's SuperAGP family can significantly
shorten their IC and system development cycles and improve time-
to-market for their end products.
SuperAGPMasterCore and SuperAGPTargetCore are synthesizable
Verilog RTL code designed to be fully compliant with the AGP 1.0
and PCI 2.1 standard specifications. Both cores are highly
modular and programmable. They enable designers to set
parameters and synthesis constraints for easy optimization to
their particular designs without modifying the RTL source code.
Integrated Intellectual Property has exhaustively verified the
cores with a testbech suite of more than 500,000 transactions
that covers all bus transaction protocols and logic state
"corner cases."
SuperAGPMasterCore and SuperAGPTargetCore perform at 1X (66 MHz
clock cycle) and 2X (133 MHz clock cycle) timing and support
mixing of AGP and PCI transactions. Cores with 4X (266 MHz clock
cycle) capabilities should be available now. Integrated
Intellectual Property has architected the cores for backward
compatibility with existing PCI designs and legacy verification
environments to leverage customers' previous engineering
investments during their upgrade process to the AGP standard.
The cores use a FIFO-based interface that facilitates
integration with users' own PCI logic and simulation models.
Users can also purchase a PCI core and verification environment
from Integrated Intellectual Property.
Integrated Intellectual Property's SuperAGP cores are available
immediately priced at $150,000 U.S. list each. In addition to
the synthesizable Verilog source code, each core package
includes synthesis scripts for bottom-up hierarchical
compilation, a user's guide with block-by-block documentation
and timing diagrams, 10 hours of consulting services for setup
and installation, and unlimited technical support by phone and
email.
Integrated Intellectual Property's SuperAGP verification
products are available immediately priced at $30,000 U.S. list
each. The environments also include a user's guide, 10 hours of
consulting services for setup and installation, and unlimited
technical support by phone and email.
www.I2P.com
Compaq Showcases Windows NT-Based Simulation Farm
(March 16)
Compaq's Windows NT-based simulation farm is a distributed (yet
shared) computing environment based on multiple Windows NT-based
Compaq Professional Workstations linked in a rack-mounted
configuration, supported by automatic job scheduling and
workload management load balancing software and running high
quality tools for simulation and verification.
The first Windows NT-based compute farm, which has been
implemented, tested and deployed by Compaq's electronic design
automation (EDA) team, delivers increased performance and fault
tolerance, lowers administration costs, and maximizes the use of
computing resources for demanding EDA environments.
The Windows NT-based simulation farm concept, which emerged as
part of Compaq's migration strategy from a Unix to a Windows NT-
based design environment, provides Compaq EDA personnel with
massive processing and memory resources not accessible with
individual workstations. The Compaq Windows NT-based compute
farm has been in production use since January 1998 and is being
used to support the design of all of the company's workstation
products. The simulation farm also allows systems administrators
to standardize system configurations and centralize
administration for significantly lower cost of ownership.
The Compaq Windows NT Compute Farm is comprised of 24 rack-
mounted Compaq Professional Workstation 8000s (six per rack) and
two ProLiant 5000 servers connected by 100 Mb FDDI collapsed
ring concentrators. Each Professional Workstation 8000 features
four 200 MHz Pentium Pro Processors, 2 GB of RAM and 4 GB of
disk space. Compaq selected the Professional Workstation 8000
for its power, scalability and its ability to be rack-mounted.
The Professional Workstation 8000's ability to address up to 3
GB of memory made it ideal for memory-intensive applications
such as logic simulation. The Professional Workstation 8000 also
features Compaq's innovative Highly Parallel System
Architecture, which delivers two to four times the memory
bandwidth and twice the I/O bandwidth of other Intel processor-
and Windows NT-based systems.
Compaq chose the Verilog-XL logic simulator from Cadence Design
Systems, Inc. as the first application to deploy on its Windows
NT-based compute farm. Rigorous integration testing was
conducted with Cadence Design Systems, Microsoft and Platform
Computing to optimize Cadence's Verilog-XL product, Platform's
LSF Suite and Microsoft Windows NT Server for the compute farm
architecture. Cadence's Verilog-XL simulator, the industry's
leading ASIC sign-off simulator, supports mixed-level design and
is linked to high-performance design composition, logic and test
synthesis. It also reduces simulation and design iterations and
simplifies tool, design data and library management.
www.compaq.com
Wave Issue 9805 4/3/98 Article 5-01