Wave Issue 9707 4/14/97 Article 4-01

***nvidia - RIVA 128 - Major Performance Improvements
in 3D, 2D and Video
by John Latta

nvidia has announced its 3rd generation product, the RIVA 128, for Real
Time, Interactive and Video & Animation. WAVE has seen initial results
from this chip and it raises the bar again in 3D and 2D performance.
nvidia has done 180 degree turn away from a special implementation of
the 3D pipeline with its nv1 and gone for the maximum performance it
can get in a mass market part - $30 in quantity. At the time this
report will be distributed the part will be only 2 weeks out of fab and
early test results are significant - the fill rate is 100 Mpixels/sec
with all features turned on.

nvidia took a risk in the design process and it appears to have paid
off. That is, it was a flagship customer of the IKOS VirtuaLogic and
Avatar hardware emulation. Using this technology in only 2 months
nvidia was able to implement the complete silicon from the ASIC
specification, do complete functional tests and begin the software
driver tests before fab - what is called Virtual First Silicon. They
claimed that Avatar allowed them to find every functional error on the
chip.

The chip has a 128 bit pipeline throughout. nvidia claims that what
they call fast and wide is critical to support not only 3D but
simultaneous 2D and video. The chip contains 3.5m transistors, and
executes at 20B operations/sec. There are 50 floating point processors
on chip and all the set-up calculations are done in FP at a rate
claimed to be 5 GFLOPS. The chip runs at 100 MHz, however, the design
is scaled such that faster clock speeds are expected to be supported.
The process technology is .35 micron with 5 layers. The RIVA 128
includes a texture cache and vertex cache. The expected performance is
5 M triangles/sec (peak with an average of 1.5M triangles - all
features turned on) and fill rates at 100 Mpixels/sec for 25-pixel
triangles. A 207 MHz RAMDAC is integrated into the chip. The chip also
supports planar YUV formats. Capabilities include: perspective
correction, bilinear filtering, lighting, 16 bit z-buffer and alpha.
The chip will support AGP and PCI

Memory interface is to SGRAM up to 4MB with 128 bits data path and up
to 1.5GB/sec bandwidth. What is important about this design is the
handling of texture memory and caching. nvidia claims an intelligent
caching algorithm which allows the chip to draw texture information
from three sources - potentially all simultaneously. In order to
achieve the fastest rate the first access is to the onboard texture
cache. If accesses are required beyond the cache the chip can go to the
SGRAM or system memory using either PCI or AGP. The SGRAM is used for
z-buffer, frame memory and texture storage.

nvidia has potentially shortened the time-to-market for a critical
component - the software drivers. Using the Virtual First Silicon
nvidia was able to move very quickly from silicon to credible
demonstrations of performance. On the show floor nvidia was showing
WinMark 97 scores of 99.6.

At WinHEC it was announced that STB will use the chip in its Velocity
128 3D product.

Both Thompson and nvidia will market the chip. Thompson will focus on
the overseas markets and nvidia will develop OEMs in the US.