The WAVE Report on Digital Media
3D --- Media Creation --- Shared Space
Published by 4th Wave, Inc.
Issue #728 10/22/97
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CONTENTS

728.1 Quick News By John Latta

H-P Terminates Pixel Flow Product


H-P will not be selling the PxFl product (WAVE 717.9) which was shown at SIGGRAPH. The Chapel Hill facility will be closing and personnel are expected to be relocated to other parts of H-P. The company will take this technology and focus it into more mainstream products. The technology and patents will be transferred to the Workstation Graphics Laboratory in Ft. Collins.

http://www.hp.com
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Microsoft Drops Transform and Lighting from DirectX 6
(October 14)

Peter Glaskowsky announced during the Microprocessor Forum that Microsoft had dropped Transform and Lighting from DirectX 6.0. This will apparently preclude these options from being accelerated in hardware in the next release.

http://www.microsoft.com

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Nintendo Wins in Court Against GE
(October 8)

Judge Alfred M. Wolin of the United States District Court for the District of New Jersey granted a motion for summary judgment Tuesday, October 7, in favor of Nintendo of America Inc. and its Japanese parent company, Nintendo Co., Ltd. This judgement threw out a patent lawsuit that had been filed by General Electric Company against Nintendo in 1995.

General Electric had claimed that certain of Nintendo's products infringed patents which General Electric had acquired with RCA. From the outset of the litigation, Nintendo asserted that GE's dated patents had no application to Nintendo's state-of-the-art video game products and that GE's claims were baseless. Nintendo advised the Court that it would seek summary judgment promptly after GE filed its suit. GE, however, insisted on and was allowed to take extensive pretrial discovery in an attempt to support its claims. After GE was allowed extensive discovery, Nintendo's motions were briefed to the Court, including the presentation of video demonstrations of the technology involved and extensive expert analysis.

On October 7, the court upheld Nintendo's position in dismissing the case.
http://www.nintendo.com

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728.2 Systems


E&S Will Supply 78 IGs to CCTT Program
(October 13)

Evans & Sutherland Computer Corp. announced that it has been awarded the Low Rate Initial Production (LRIP) contract to supply 78 ESIG-4530 image generators to Lockheed Martin Information Systems. Lockheed Martin is the prime contractor to the United States Army's Simulation Training and Instrumentation Command (STRICOM) for the Close Combat Tactical Trainer (CCTT) program. The LRIP contract is valued at $16.75 million. The image generators will be integrated into simulators for armored and mechanized infantry simulation training. E&S will commence unit deliveries in March 1998 for this phase of the CCTT program. As part of the pre-production phase now underway, E&S has already delivered 134 ESIG-HD/3000 image generators and two synthetic terrain databases, each representing land areas of 100 x 150 kilometers. The potential exists for significantly more unit orders once the LRIP phase is complete and the CCTT program enters full production in 1999.

http://www.es.com/

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728.3 Computers

Gateway 2000 Announces AGP System for Under $2,000
(October 7)

Gateway 2000, Inc. has announced its G-Series PCs. The G6-233 includes a Pentium II processor, Intel's 440LX chipset with AGP support, a 17" (15.9" viewable) EV700 monitor, nvidia's 4MB AGP graphics accelerator, 2GB Ultra ATA hard drive, Telepath modem with x2 technology, 32MB of SDRAM, wavetable audio with Altec Lansing speakers and a 12x minimum/24x maximum CD-ROM for under $2,000.

http://www.gateway.com
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NEC to Ship Handheld PC Using Windows CE 2.0
(October 13)

NEC Computer Systems Division (NEC CSD) announced the development of a new handheld PC that uses Microsoft Windows CE 2.0. As part of the NEC MobilePro handheld personal computer series, this PC will feature a form factor unlike any other, with a typeable keyboard, larger display size, and be light weight, at under 1.5 pounds. It will be available mid-November.

http://www.nec.com/

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Sharp Announces Color HPC with Windows CE 2.0
(October 13)

Sharp Electronics Corporation announced the Mobilon, a new line of handheld PCs using the Microsoft Windows CE, Version 2.0 operating system. Sharp's new Mobilon line includes a color screen unit, digital camera option, audio record feature, seven "one-touch" application keys and other features exclusive to Sharp. In addition to the 8MB color model of the new line (HC-4500), the new Mobilon series also has two monochrome units with 16-grayscale LCD (4MB HC-4000 and 8MB HC-4100) and an optional PC card digital camera designed specifically for the Mobilon series. This camera, the CE-AG04, enables users to capture and transfer digital images from their handheld devices to and from a PC, add voice messages and be used to send multimedia e-mail. The Mobilon will be available in the U.S. in the fourth quarter of 1997.

http://www.sharp-usa.com

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H-P Announces Windows CE 2.0 Product With HP 360LX
(October 13)

Hewlett-Packard Company has introduced the HP 360LX palmtop PC with Microsoft Windows CE 2.0. The HP 360LX offers a full-width, 16-greyscale, high-contrast screen with natural-white backlight and enterprise management features. The HP 360LX palmtop PC also comes with 8MB of RAM; 10MB of ROM; and an improved Hitachi microprocessor. The HP 360LX has an estimated street price of $699 (U.S.).

In late 1997, HP expects to further enhance its palmtop PC line with the HP 620LX, a color-display model.

In early 1998, HP expects to deliver software to manage the HP 360LX palmtop PC as a component on the network using HP TopTools and other DMI-compliant management applications. HP TopTools will lower a corporation's total cost of ownership of enterprise computing products while giving network administrators a standardized means of managing computing assets in the enterprise.

http://www.hp.com/handheld

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728.4 Cards

I/OMagic Introduces 3DfX Voodoo Rush Card
(October 9)

I/OMagic Corporation has released MagicRush 3D based on the 3DfX Interactive Voodoo Rush chipset. MagicRush 3D also includes the 128-bit Alliance ProMotion AT3D 2D/3D multimedia processor and 6MB EDO DRAM.

The MagicRush 3D will reach stores in mid-November and is expected to retail for $179.00.

http://www.iomagic.com/

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E4 Rolls Out CoolView 3D
(October 8)

DVD board manufacturing company E4 announced the availability of CoolView 3D a 2D/3D graphics and video accelerator based on the Nvidia RIVA 128 chip and 4MB of SGRAM. CoolView 3D is available now for OEMs and will ship to retail markets in November at a retail price of $199.

http://www.e4.com/

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Canopus Uses RIVA 128 Chip from Nvidia
(October 15)


Canopus Corp. announced Total3D 128V, a 128-bit graphics accelerator powered by the RIVA 128 chip. The card includes a software bundle which has Micrografx's Simply3D 2 LE and PLATINUM Technology's VRCreator/Learning Edition. These applications use Direct3D and Total3D 128V to speed the creation of 3D models and VRML 2.0 worlds. A game sampler with demo versions of the latest Direct3D titles plus trial version of video applications round out the Total3D bundle. These trial versions include VDOnet's VDOPhone Trial 3.0 for video conferencing, Ulead's MediaStudio Pro 5.0 for video editing, and Vivo Software's VideoNow 2.0 for streaming video on the Internet. With a list price of $249, Total3D 128V will be available in November for $229 direct from Canopus.
http://www.canopuscorp.com/

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AccelGraphics Wins Acer America for AccelSTAR II
(October 6)

AccelGraphics, Inc. announced that Acer America Corporation selected AccelGraphics' new AccelSTAR II graphics subsystem for its AcerPower workstation. The AccelSTAR II uses the 3Dlabs' PERMEDIA 2 processor that was also announced on the same day.

AccelGraphics has other OEM relationships with Gateway 2000, Epson, Hewlett-Packard, Hitachi and Samsung.
.
http://www.accelgraphics.com

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728.5 Chips
 
IKOS Wins Rendition Business
(October 6)

IKOS Systems Inc. announced that Rendition Inc. has selected the IKOS VirtuaLogic emulator and consulting services for early software development and system verification of its next generation 3D graphics chip. Rendition is utilizing a five-board VirtuaLogic emulator, with the capacity to emulate up to 1 million gates, to verify the graphics chip.

http://www.rendition.com/

http://www.ikos.com

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728.6 Home Entertainment

Psygnosis' Releases Title for AGP
(October 8)
G Police has been tuned for Intel's Pentium II processor platform including AGP. To be released on Nov. 4th it will be priced at $49.99.
 
http://www.gpolice.com/
http://www.psygnosis.com/
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Dynamix Released 3D Ultra Pinball
(October 10)
Dynamix, a division of Sierra On-Line Inc., has released 3D Ultra Pinball: The Lost Continent. This sequel, following Sierra's 3D Ultra Pinball and the popular 3D Ultra Pinball: Creep Night, will continue the great tradition of the 3D Ultra Pinball series. 3D Ultra Pinball: The Lost Continent features over 20 different inter-linking tables with fully rendered 3D graphics and characters.
 
3D Ultra Pinball: The Lost Continent is available on a hybrid CD-ROM for Macintosh and Windows for an estimated street price of $44.95.
http://www.sierra.com /
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728.7 - Conference Report - Microprocessor Forum
October 14 - 15, 1997 By John Latta

To some this is a dry conference with excessive discussions of superscalar design, out of sequence execution and floating point extensions to X86 architectures, yet, what was outlined here will set the stage for computing for the next 10 years. In fact, this was the 10th anniversary of the conference. The first conference, at the Red Lion Inn 10 years ago, was attended by only 250. This conference was packed with 1,200. With the roll out of the IA-64 architecture by Intel and HP the stage is being set for the next generation of computing. Many of the talks also have significant implications to mainstream computers and 3D.
 
The conference is a reflection of Michael Slater's style and approach, the founder of MicroDesign Resources (MDR) and Microprocessor Report. He combines both a laid back image with a cutting and insightful evaluation of the industry. He has an ability to get to the core of issues and tell it like it is. Not infrequently he has been on the backside of Intel and at times relations with Intel and his publication (Microprocessor Report) have been strained. Yet, Intel recognizes that his newsletter and views do much to shape the industry and the actions of others. Thus, there is a benign tolerance by Intel of MDR. The first day of the conference was an excellent illustration of this. Intel was using the conference to "announce" both the IA-64 and reveal the roadmap for future Intel processor generations. Consistent with Intel's obsession with secrecy it would only leak out a bare minimum in very well rehearsed and scripted talks. When asked for the slightest hint of their future plans, outside of these bounds, Intel looked somewhat silly in their verbal game playing. A number of the Intel speakers even spoke of the consequences of facing the wrath of the minions of Intel PR types sitting in the back of the room. Thus, it was not infrequent that MDR would ask for the obvious and Intel would respond with nothing more than trivia. One response even went so far as to treat the impact of simple addition as a secret.
 
Intel not only rolled out the IA-64 but set new heights in PR share - a measure of the relative participation of PR in a product announcement. Here are the statistics:
 
Intel AMD Cyrix
87% 6.6% 6.6%
 
Intel had 13 from PR at the conference compared to 1 each from AMD and Cyrix even though the Chairman and CEO of AMD gave the keynote. It appears that when only the paranoid survive only the paranoid are paranoid.
 
We report on talks below.
 
AMD - Jerry Sanders - Keynote
Jerry took a combative posture in his attacks on Intel. He stated that when they acquired NextGen it was his charge to AMD that they must get 30% of the of the X86 market by 2001 when the unit volume will be from 140 - 160m units. He described this as creating a new world order for Windows. Their challenge is to ship 15m units by 1998. Yet, AMD has been tripped up recently by its inability to execute. Yields have been lower than expected and the stock recently took a beating. Yet, Jerry took both an upbeat but cautious tone. Much centers on the 30% share goal. They must reach a minimum level of industry performance or it will be impossible to generate the cash required to keep fab lines current with process technology. In an interesting slide he showed how Compaq with 10X the sales of AMD, that AMD nearly the same amount as Compaq. AMD's combined capital and R&D expenditures are over $1b.
 
Jerry used this talk to lay out AMD's strategy for the future on how it will compete with Intel. Its K6 processors are described as the "Microprocessor for the Masses." He was blunt in his assessment that AMD is in lock step with Intel on its visual computing initiative and, in fact, used a direct quote from Andy Grove's 1996 talk at COMDEX. With this their roadmap was laid out. At the center of the strategy continues to be Socket 7. This was common with all of the Intel competitors. Slot 1 is Intel's way of not only extending the technology but also keeping others out of its markets. In response he saw three different approaches to keeping Socket 7 alive which will be discussed in the later papers.
 
Today the AMD-K6 MMX Enhanced processor has the following attributes:
 
.35 micron
162 mm square die
8.8m transistors
233 MHz
1H 1997
 
By the second half of 1997 they will move to .25 micron technology and implement the following:
 
.25 micron
68 mm square die
8.8m transistors
266 MHz
2H 1997
 
This will support the Super7 interface by Q4 which will include 133MHz AGP off of the North Bridge and a 66 MHz Socket7 interface.
 
Next comes the AMD-K6 in 1H98 that has the following characteristics
 
.25 micron
81 mm square die
9.3 m transistors
300 - 350 MHz
1H 1998
 
The interface will include a 100MHz to Socket 7 and L2 frontside cache, 100MHz to main memory and 133MHz to AGP.
 
Most importantly he announced the AMD-K6 3D Processor with the following attributes.
 
.25 micron
135 mm square die
21.3 m transistors
350 - 400 MHz
2H 1998
 
This includes on-chip L2 cache of 256K bytes and directly avoids the Slot1 L2 cache issue.
 
Equally as significant Jerry announced with the AMD-K7 processor that the bus interface would move to DEC's EV6 bus protocol, from the 21264 Alpha microprocessor, on a Slot A configuration that is mechanically identical to Intel's Slot 1. This would surface in 1999. Yet, AMD faces an important problem - how to get core logic if it is the only company using the EV6 bus. AMD, in later comments, was confident this would happen, we are less so.
Jerry concluded that at a $1,699 price point that AMD could offer significantly more PC for the money. It was claimed that the system would run approximately 1/3 faster at the same clock speeds and provide more capabilities.
 
He stated bluntly that in 1998 AMD would have better 3D capabilities than Intel.

 

 
Michael Slater - MDR
Michael then introduced the session on the competitive strategies for x86 processors with a short talk. Consistent with Jerry's announcements, which proceeded him, Michael stated that 3D has generated broad interest in floating point where up to now there has been no driving demand for FP on microprocessors. This has now become a key element in the extensions to the instruction sets. The sessions to follow would only reinforce this. The downside is that nothing is consistent between the players.
 
Michael also stated that MMX is a done deal. However, it was not MMX that was driving its adoption but the additional features of the processors that use it, in particular, larger caches and faster clock speeds. It was stated that virtually all the applications that use MMX are those that are based on hand tuned code supplied by Intel.
 
At the same time he described how the market growth is at the low end. Credited with a major win is Cyrix on the Compaq Presario 2100 and 2200. Michael stated this is an example of the first successful PC with a high level of integration. With Intel's focus on higher price points the low price PCs provide a market opportunity for others, yet, he also cautioned that it is hard to make money at the low end of the market.
 

 

Bob Colwell - Intel - Evolution of IA-32 System Design
 
Before the IA-64 announcement was made Intel described how IA-32 (read Pentium II) would continue to evolve and thus create two distinct product families. The charts indicated that this product family would go to 2005. Extensions would include: larger caches and faster microarchitectures. It was estimated that cache densities could reach 32Mb by 2005. With Slot 2 the IA-32 family would support up to 4 way MP. At the same time Slot 2 would not replace Slot 1 but meet the needs of the server and other high performance markets. The talk concluded by stating that IA-32 would support all but the "highest end segments" leaving the positioning of the IA-64 announcement to follow later in the day.
 
Greg Favor - AMD
This talk was an elaboration of the keynote with more details on the K6 processor family roadmap. Key points are that the major core logic vendors are behind the move to 100MHz local bus and AGP. These include: ALi, National, SiS, VIA and AMD. The 3D extensions to the instruction set allow for multiple FP operations per clock. It uses a SIMD architecture with 2 FP values per 64bit register and memory operation. The MMX registers are used. They claimed full Microsoft support and the fact that their approach is fully optimized for DirectX and in particular D3D and OpenGL. No performance estimates were made.
 

 

Robert Maher - Cyrix
Their next processor is the 6x86MX processor due in Q1 1998. This includes 100MHz bus and AGP support. Next is a processor based on the Cayenne Core. It has 64Kb of L1 cache, uses .25 micron process technology and a dual issue FPU pipeline. This core fits on a 65 mm square die and due to go into production in 2H 1998. They claim the design supports up to 1GFLOP performance. Other features in the FP set include scatter/gather operations for vectorized floating point, and reciprocal and reciprocal square root for lighting calculations. In geometry calculations they claim 3x the performance increase. Cyrix will also provide an OpenGL driver. The talk was summed up with a performance claim: 10m meshed triangles/sec peak performance with both geometry and lighting.
 

 

Glenn Henry - Centaur Technology
Centaur Technology is a part of IDT and the WinChip C6+ is a part of their strategy to penetrate the x86 market. This part is focused on the low end of the market. Glen made no bones about their target of the tier 3 suppliers of sub $1,000 PCs. In fact, their reference platform is at $750. It was claimed that there are 10's of qualified motherboards and 4 BIOSes available. The WinChip core is a lean and mean approach to x86 compatibility. It uses .35 micron technology and fits on only an 88 square mm die. A 180 MHz part is only $90 and a 200 MHz is only $135, both are shipping now.
 
The next generation C6+ is due 1H 1998 with a tape out on November 15. Samples are expected in Q1 1998 and volume expected in Q2 1998. There are 53 new instructions and these are focused on 3D. A major difference with the Centaur approach is they have added 22 new FP registers. Glenn claims they are working closely with Microsoft for D3D support. Supporting their extensions will be transparent to applications.
 

 

John Crawford, Intel, and Jerry Huck, H-P
This was the high point of the conference with the roll-out of the next generation instruction set for the IA-64. They have termed their new architecture: Explicitly Parallel Instruction Computing (EPIC). With a much expanded register set (128 GRs and 128 FPs) and with independent execution units they feel that it is possible to have a scalable family of microprocessors which can continue to add execution units. Key to this design is a new instruction format that is based on 128 bit bundles. Bundles contain 3 instructions and a templet that has support for both predication and speculation. At the center of the architecture is a very cooperative relationship between the compiler that exposes the highly parallel machine to the code and the microprocessor design. The output of the compiler translates the code into individual execution instructions which are conditional based on the original code base. It is claimed that Predication execution removes branches and removes mispredict penalties. Speculation allows one to separate load behaviors from exception behaviors. This is claimed to reduce the impact of memory latency.
 
Just because this was an Intel talk on the future it generated much more interest than the others at the conference, however, little more than the most scant details were released.
 

 

Fred Pollack - Intel
To help flush out the impact of the IA-64 announcement Fred provided Intel's roadmap. This was clearly another highly sanitized low information content presentation but it did provide some insights.
Intel is positioning the IA-64 for only the highest end applications - best called a mainframe and workstation killer product. IA-32 will continue to be the mainstream product. There will be many forms of the IA-32 products including those supporting mobil, mass market and servers market segments.
 
Merced will be the first IA-64 product that will go into production in 1999. Intel announced that it is working on the next generation IA-64 chip and this will go into production in 2001 and will have 2X the performance of Merced but use the same process technology - .18 micron. It is not expected that the IA-32 and IA-64 products will converge until 2003. Intel will sell and manufacture the IA-64, not H-P. When asked Intel stated that IA-32 code would run on an IA-64 at the same rates as the "mainstream IA-32 processors."
 

 

During a panel discussion Microsoft stated that they would have a version of Windows NT which fully supports Merced when it ships along with a compiler.
 
Embedded Microprocessors
There is new life in this market. Jim Turley of MDR claims that the average home has 100 microprocessors in it. This is a very different market from the mainstream PC market. While Intel dominates PC microprocessors the comparable situation does not exist in the embedded world. Designers have many options and at this session 7 new microprocessors were announced. It is outside of the scope of this report to go into these in detail. Sun did announce the microJava 701 a second generation Java centric processor. It provides for the direct execution of Java bytecode instructions. It seems ironic that designers have barely become familiar with microprocessors based on the picoJava 1.0 cpu core and here comes another one. Digital announced the StrongARM SA-1500 that is the StrongARM with an Attached Media Processor (AMP). National Semiconductor announced a Pentium Class processor (NS586) for Internet applications. Pushing their objective of a complete system on a chip this microprocessor has performance of a 90MHz Pentium for only $25. It runs at 100MHz and 133MHz, has 930,000 transistors, fits on a 25.8 mm square die and uses .35 micron process technology. The targeted applications include Internet appliances, remote access terminals and TV based Web access devices. The implementation had neither an FPU nor MMX support. An example was shown of how this core could form the foundation of a system chip that used the core being presented here. One area of continuing debate in this session is the desire to keep the code base small and thus the amount of memory required in these cost sensitive applications. Given the CICS nature of the Pentium this is certainly not the case. However, the appeal of the processor is its ability to run many applications. Our sense from this session is that this may be a distinct advantage, however, it is not a sufficiently compelling reason to justify a mass migration to x86 cores as embedded applications.
 

 

Allen Roberts - Direct Rambus
Rambus rolled out its new memory standard and with Intel's support this seems to have captured the market attention of all PC based systems. During the panel discussion afterwards alternative high performance memory technologies were represented and no one would state that their technology would have a strong market position against Direct Rambus when it is selling in high volume.
 
Direct RDRAMs provide 1.6GB/sec of performance. The interface has been widened to 2 bytes and the channel frequency has been upped to 800MHz. There is now independent row, column and data resources. The presentation went into detail on the transactions, in considerable visual detail, that we will not repeat here. Rambus also funded lunch, which they touted as a free lunch and released technical details in the handouts provided on every seat. An advantage touted for this memory is the ability to add as little as one memory chip at a time and not add banks of 8. In response to a question it was disclosed that it may be necessary to add a heat spreader due to the fact that all addressing in a specific region of memory could raise the thermal profile of the chip. The die size is comparable to SDRAM and RIMM modules were revealed which are comparable to DIMMs. In a 65MB configuration Direct RDRAM will consume 4.3 watts compared to SDRAM at 100MHz at 4.5 watts. A roadmap was discloses which showed 64Mbit parts in mid-1998, 256Mb in early 2000 and 1Gb in late 2001. In spite of the fact that many saw this as the future everyone seemed to rumble about the royalties they must pay for these chips.
 

 

Doug Beard - Cyrix MXi x86 Processor with Integrated 3D Graphics
This was a more detailed talk that continued on the previous day's presentation. The objective of the MXi processor is to provide a mainstream processor for the desktop in the 2H 1998. The key features include the Cayenne core disclosed yesterday, support for SDRAM with up to 2GB/sec memory bandwidth and performance consistent with 4X AGP and support for 66MHz AGP. This chip continues the high level of integration present on the Media GX processor and a MXi block diagram was shown which included only the processor and a South Bridge to complete the system. Touted as integrated 3D graphics features were bi and tri-linear filtering, alpha blending, MIP mapping, AGP software compatibility and Z-buffering. The graphics will support up to 1600 X 1200 and includes a 2K texture cache. The chip is claimed to be fully D3D compliant. Performance figures include 2m triangles/sec and a fill rate of 120m pixels/sec with perspective correction, z-buffering and bi-linear filtering. Tape out is scheduled for 4Q 1997 with production in 2H 1998. The chip has 9m transistors and is accomplished on 90 square mm and .25 micron process technology.
 

 

Ronda Collier - S3 - ViRGE/MXi
This chip integrates ViRGE 3D, with 2D and embedded DRAM for the portable market. The feature set of the chip is impressive: leading edge 2D, embedded RAMDAC, 3rd generation 3D engine, television support including Macrovision and DuoView display support. A major challenge to the design team was the integration of on-chip memory. S3's approach is a new memory type they called S3RAM that has 1.36GB/sec performance. The 3D capabilities include perspective correction with divide, bi and tri-linear filtering, alpha blending, z-buffering and depth cueing. The chip is one of the first to fully support multiple monitors and it has separate VGA control blocks for separate displays. In fact, the portable market is an obvious one to take advantage of the multiple monitor capabilities of Windows 98 and NT 5.0. Ronda described DuoView support as a significant design challenge. They also characterized the TV-Out design as advanced which includes a Flicker Filter that has 3 or 2 programmable taps. There is also a 9 tap Chroma filter. Output is in NTSC or PAL in SVideo or Composite formats. The embedded memory architecture is 128 bits wide and is based on 8 banks of 16K by 128 memory array. We found it striking that the S3RAM architecture has redundancy repair so that the yields of this chip with memory would match that of ASIC chips. There are 3% spare columns and rows that can be repaired at the metal or poly fuse level. The chip details include: 18m transistors, a die size less than 150 mm square in a 256 pin PBGA package and it used .25 micron technology. The ViRGE/MXi is also pin compatible with the ViRGE/MX. When using 3D the power consumption is less than 1.2 watts and substantially less than 1 watt with only 2D. It was also stated that the chip has 1/2 million gates. The chip will ship in Q1 1998 and pricing has not been determined. One of most striking disclosures came from the question and answer session. S3 claimed that the design team of only 9 engineers took 6 weeks to do the concept design, 4 weeks for the functional verification and 8 weeks for the timing. FAB was released in 30 days from tape out.
 

 

Les Kohn - C-Cube Microsystems - DVx MPEG-2 Video Codec
 
It is a major achievement to have both an MPEG-2 coder and decoder on one chip. This chip is claimed to span the quality requirements from broadcasters to PC applications. Pricing was not disclosed but it was stated that this part would not likely make it into mass market products for 2 years. The chip is quite sophisticated with a 32bit MicroSPARC controller engine embedded. The instruction cache is 16Kbytes. The chip is also designed to be scalable where 4 or more chips can be combined to support HDTV. The chip has 5.4 million transistors, fits on a 162 mm square die, consumes 4.7 watts in a 352 pin BGA package. Samples are available now with production in December.
 
Gerald Pechanek - BOPS - ManArray
In addition to the Intel announcement the previous day this presentation was the technology disclosure of the conference. Claiming to support 50B operations per second this sets a new standard for processing scalability and performance. BOPS is a team of engineers which originally worked on the IBM Mfast processor which was internally killed at IBM. Using innovative techniques, which we do not has space to repeat here, BOPS has developed a scalable architecture which supports a cluster building block approach for massive parallelism. The basic building block has a PE with local memory. A 2 X 2 configuration this is connected by a Cluster Switch (CS). A Sequence Processor (SP) provides control. Within the PE execution is accomplished on long words in what is described as eVLIW. The PE can operate in SIMD, Vector and Multiple-SIMD modes. The combination of the ManArray architecture and these components will allow scaling to 4 X 4 X 4 cores and into even larger systems. The key to effectively using this architecture is software. Gerald described programming as fun and took some jest from the audience. It was claimed that a ManArray could be programmed conventionally but this loses the major advantages it provides. The advantages of a 4 X 4 matrix multiply was shown to go from 144 operations which used conventional methodologies to only 2 cycles using a 4 X 4 ManArray with dual 16 bit packed data and eVLIW instructions. BOPS is developing a library of optimized applications for 3D, MPEG encoding, audio and other areas. The first product is Kitty Hawk that is a 2 X 2 array. It has 181K gates in the cluster, with 16K Bytes in the SRAM and uses 13.8 square mm at .25 microns. The peak instruction rate is 12.8 BOPS. This chip will be available in 1H 1998. The chip will run at 100MHz and is scalable to 200MHz. A 4 X 4 core would fit into 729K cluster gates, include 64KBytes of memory and at .25 microns cover 55.9 square mm. The average power would be 5 watts and the peak processing would be 50 BOPS. The company is looking to license the BOPS technology to a limited number of partners.
 

 

There were no new blockbuster 3D chips announced. However, the pace of ASIC complexity continues. There seemed to be an underriding issue that the tools for design are not good enough to support the design demands that continue to grow. Yet, in spite of this, tool limitations do not seemed to slow the pace of innovation.
 
728.8 - Points to Ponder - Microprocessor Forum
by John Latta
 
The positioning of IA-64 vis-a-vis IA-32 seems to put the best spin on protecting H-P's RISC workstation business and Intel's existing Pentium II businesses. It is also likely that the performance of IA-64, when running legacy code, will lag behind some clock speeds and versions of the IA-32 chip. This could endure until applications are ported to the new instruction set and been optimized for the IA-64 microprocessor. Intel is preparing for the transition period. In many respects Intel can do what it likes because it is highly unlikely that it will have any competition in this performance space until well after IA-64 is launched. Further, one could expect that Intel has done everything in its power to lock up the IP around the IA-64 so that any clones would face nothing less than a riot of attorneys at the slightest hint of a competitive response.
 
The emergence of several MMX II extensions from the x86 crowd is a good news bad news story. The good news is that 3D stands to gain major performance improvements. The bad news is that each are all different and it is highly questionable how much industry support there will be to use these extensions. As we well know game developers move first when silicon arrives and then when the installed base is significant. Now the issue is even more complex because the extensions have to first get Microsoft then developer support.
 
It was interesting that all the x86 competitors, Intel, of course, excluded, stated that they would license their FP extensions. However, this comes only after they each had announced the extensions and are well along in implementing them. This gives us reason to believe that these instructions are not locked in concrete. Even Cyrix indicated that they could change their op codes to match Intel's when the MMX II instructions are announced.
 
During the panel discussion following the IA-64 announcement Intel took a position on MMX II much like the proverbial bump on a log - refusing to comment outside of the script and just smiling.
 
We see a number of issues:
There is the potential for many conflicts by having such disparate implementations of FP MMX II for 3D geometry acceleration. From different op codes to even IDT's implementation of distinct registers, this could lead to a nightmare of options and a fragmented market that ends up not getting used at all.
 
Intel is confident that its solution will prevail in MMX II. They are adamant that in spite of the appearance of a more rapid pace at the x86 companies they will be first with the best to market. A key point is that Intel made an important decision in its implementation of MMX II. That is, with MMX they pre-announced the technology and licensed it. Thus, it rapidly became an industry standard that is now universal. However, with MMX II this is clearly not the case because Intel will not announce MMX II in advance. We see that only the market will suffer and this could impact the 3D performance ramp.
 
Microsoft is really the gate keeper on MMX II and the competing 3D acceleration solutions. What they chose to support is likely to determine if one method survives over another. Microsoft could be a broker and appeal to the x86 crowd to have a common implementation but this is highly unlikely to happen. Microsoft is the only disinterested 3rd party in the bunch and, in fact, the only one capable of standing up to Intel.
 
It is highly unlikely that any of these extensions will get much support in 1998. That is, none will have silicon in time to influence DirectX 6.0 that will be the foundation for Q4 1998 sales. This delay only supports Intel's market advantage by allowing it to gain more support and announced its solution as others fight for prominence. Further, as we report in this issue of WAVE, there will be no support in DirectX 6 for geometry acceleration.
 
There is a conflict shaping up between Intel's market focus and the rest of the x86 crowd. That is, the alternate suppliers are focused on the low end of the market - the sub $1,500 PC and many are intent on the sub $1,000 PC. To date Intel has not shown any interest in this market segment. AMD has this in their sights and is aggressive in its relentless pursuit. Microsoft can ill afford to ignore the emergence of this market segment as it enlarges the potential penetration of Windows. At the same time Microsoft is faced with an increasing development and support burden to enable many variants to implementing immediate mode 3D geometry acceleration which will do much for the alternative companies to differentiate themselves at these price points. Intel will clearly be pushing for maximum impact of MMX II when it rolls out. Thus, what Microsoft says, by virtue of its support, will say much on how this market conflict is resolved. We strongly doubt that Microsoft will ignore the potential of the sub $1,000 PC, especially when this is predicted to reach 50% of the US retail sales.
 
Raising the geometry engine performance level a factor of 10 has major implications on the use of 3D on PCs. From a game developer's perspective this would allow much more sophisticated models including humans with lifelike appearances. As the polygon performance and rasterizer performance continues to increase we expect that this will only accelerate the move to non-polygon surfaces. The key here is reaching the point where there are as many polygons on the screen as there are pixels.
 

 

It is clear that Intel's message that visual computing is important to the future of the computing industry has been received. All the mainstream microprocessor companies have the 3D religion. In the process the seeds of a war of fratricide have been planted. Unfortunately the likely winner will be the overwhelming market leader - Intel - as it walks over the bodies of the combatants.
 
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Copyright 1997 4th WAVE, Inc.

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